FlexRay was developed by a consortium of manufacturers to provide a deterministic, fault-tolerant and high-speed alternative to CAN. Now standardized as ISO 17458, FlexRay supports data rates up to 10 Mbit/s on two independent channels for improved fault-tolerance. FlexRay uses a combination of event triggered and time triggered communication, ensuring that network nodes cannot gain uncontrolled network access to signal events, and instead must access the network using a pre-determined time slot to transmit each message using TDMA in what is known as the Communication Cycle.
PicoScope software can decode and display many cycles of FlexRay data in both a table format and a color-keyed trace, time-aligned with the data signal.
A FlexRay bus consists of differential twisted pairs of shielded or unshielded cable connecting a transmitting node and one or more receiving nodes. Each differential pair must be terminated at each node with a resistance between 80 and 110 ohms. The bus is bidirectional, so each node requires both a transmitter and receiver combined in what is known as a bus driver. The two signal wires are denoted Bus Plus (BP) and Bus Minus (BM) and physical signal transmission is based on the voltage difference between these two wires, where Vdiff = BP–BM.
The FlexRay Electrical Physical Layer Specification defines four bus states, two of which are recessive and two dominant. The recessive bus state has a differential voltage of 0 volts and the dominant state has a differential voltage not equal to 0 volts. The four bus states are: Idle; Idle Low Power; Data_0 and Data_1.
In the Idle bus state, both BP and BM are driven to a nominal 2.5 V, giving a 0 V differential voltage. If a node is in its low power state (Standby, Sleep, Go-To-Sleep), the Idle Low Power bus state is used, which also has a 0 V differential voltage, but the two bus wires are in this case at a nominal 0 V level. The Idle state is a defined length of time used by each node to maintain clock synchronization. The smallest unit of FlexRay time is a “macrotick” and the FlexRay controllers use the idle time to synchronize themselves by adjusting their local clock so that the macrotick occurs at the same point in time on every node in the network.
In the dominant Data_0 bus state (which represents logical state 0 or LOW), BP is driven to 1.5 V and BM is driven to 3.5 V, giving a differential voltage of –2.0 V. In the Data_1 bus state (which represents logical state 1 or HIGH), BP is 3.5 V and BM is 1.5 V, giving a differential voltage of +2.0 V.
FlexRay uses non-return to zero (NRZ) bit coding, in which the voltage level changes only when there is a change in the corresponding logic level, so there can only be two data states on the bus, LOW (0) or HIGH (1).