CAN XL is the 3rd generation controller-area network protocol, building on and supporting backward compatibility with Classic CAN and CAN FD networks. It is targeted at in-vehicle networks, connecting multiple controllers and sensors using a single differential-mode bus. Due to the high level of robustness and use of the bus topology with minimal need for wiring, the controller-area network protocols are increasingly finding their way into new industrial applications.
The CAN XL protocol is governed by the CAN in Automation (CiA) group. https://www.can-cia.org.
CAN XL provides support for higher data bit rates and longer data payloads than its predecessors, allowing transfer rates up to 20Mbit/s and up to 2048 bytes per frame. In order to support the higher data transfer rates, a new CAN SIC XL transceiver type has been introduced; providing fast signal edges, low ringing, and symmetry required for the higher speed data transfer.
CAN XL can still be used with typical CAN, High Speed CAN or CAN SIC transceivers on mixed-mode buses or if a high bitrate is not required for the application.
The higher bit rate and data payload capabilities allow CAN XL to bridge the gap between CAN FD and Automotive Ethernet 100BASE-T1. CAN XL provides support for Ethernet tunneling and is designed for integration into TCP/IP network systems.
CAN XL makes use of a differential two-wire bus, consisting of CAN High (H) and CAN Low (L) signals.
The actual signal voltage levels are dependent on the bus topology and the transceiver type used (i.e. whether the bus is comprised of only CAN XL devices, or a mixture of CAN XL with Classic CAN and/or CAN FD devices).
The CAN XL frame consists of an arbitration phase, an XL data phase, and a second arbitration phase.
During the arbitration phases, frame bits are transferred at the ‘nominal’ bit rate, typically up to 500kbit/s. The XL data phase is usually transferred at a much higher bit rate of at least several megabits/sec, known as the XL data bit rate.
There are two logic states; Logic 0 and Logic 1. During the bus idle and arbitration phases, the Logic 0 is represented by a ‘dominant’ state, while logic 1 is represented by a ‘recessive’ state.
A recessive state is achieved when the bus is not actively driven, while the dominant state is achieved when at least one node is driving the bus. This provides for an arbitration mechanism to take place by means of allowing a dominant bit from one node to override a recessive bit transmitted by another, each node must actively read the bus state while transmitting and immediately cease transmitting if the bus state does not match that transmitted. In that scenario, another node has ‘won’ arbitration.
Arbitration can only take place during the arbitration phases, and only one node may transmit on the bus during the CAN XL data phase at one time.
A bus will idle in the recessive state typically with CAN H and CAN L signals both around 2.5V, noting that the differential voltage is at or close to zero. During a dominant state, CAN H is driven towards 5V while CAN L is driven towards 0V, resulting in a positive differential voltage.
The CAN SIC XL transceiver is capable of being operated in a ‘slow’ mode and a ‘fast’ mode. Slow mode makes use of the dominant/recessive signaling scheme that is mandatory during the arbitration phase.
Where XL data bit rates are upwards of several megabits/sec, it is often necessary to switch the transceiver into ‘fast’ mode. During fast mode, the ‘dominant’ and ‘recessive’ states are replaced by ‘level_0’ and ‘level_1’ states respectively. The level_x states are transferred in a push-pull drive mode and at slightly different voltage levels to support the higher data bit rates.
Where a CAN SIC XL transceiver is used and ‘fast’ mode is required, it is necessary for a node to be able to command its transceiver to enter/exit ‘fast’ mode.
To maintain pin and backward compatibility between transceivers, it was preferred not to add an additional control signal to support this function.
Instead, the data encoding method used on the TxD pin from the node to its respective transceiver is used to make the switch. During ‘slow’ mode, the data is transferred using non-return to zero (NRZ) encoding as is typical for all prior generations of CAN. During ‘fast’ mode, the data is transferred using pulse-width modulation (PWM) encoding, where the duty cycle of each PWM symbol represents the bus state.
The CAN XL decoder in PicoScope7 supports both NRZ and PWM subcoding.
CAN XL implements two bit stuffing schemes, dynamic stuffing which is applicable during the first arbitration phase of a frame, and fixed stuffing which is applicable during the XL data phase. No bit stuffing is present during the second arbitration phase.
Dynamic bit stuffing is consistent with that used in Classic CAN and CAN FD frames, where if at any point five consecutive bits of the same logic level are present, an additional bit called a stuff bit is inserted into the bitstream. The stuff bit has the opposing logic state of the bit that preceded it, providing a guaranteed signal edge transition in the bitstream allowing all receivers to synchronize to that edge.
Fixed bit stuffing is used during the CAN XL phase, starting with the DL1 bit in the ADS phase. A stuff bit is inserted into the bit stream at every 11th-bit position, regardless of the bit pattern that preceded it. The logic state of the stuff bit always opposes that of the preceding bit.
Start of Frame. Single dominant bit to mark the start of a CAN, CAN FD or CAN XL frame.
Frame priority identifier. 11-bits long.
For Classic CAN and CAN FD devices with 29-bit ID fields, this represents the upper 11 bits (ID [28:18]).
It is during this phase that the arbitration mechanism allows a higher priority node to override transmission from a lower priority node that may have began transmitting at the same time.
For Classic CAN frames this is the Remote-Terminal Request (RTR) flag, indicating that a device, usually a controller, is requesting a message from another device on the bus identified by its priority ID.
For CAN FD and CAN XL, this is the Remote Request Substitute (RRS) flag, which is a static dominant bit as remote frames are not supported in CAN FD and CAN XL.
Identifier Extension Flag. This flag is only available in Classic CAN and CAN FD frames to indicate whether a 29-bit priority ID is being used. If so, then the remaining 18-bits of the priority ID follow (ID [17:0]).
For CAN XL frames, 29-bit priority identifiers are not supported thus this bit is always transmitted as a static dominant state.
FD Frame flag, this indicates whether the frame is in FD (or greater) format. This bit is always transmitted in recessive state for CAN FD and CAN XL frames.
For CAN Classic frames, this same bit is referred to as reserved bit ‘r0’ and is always transmitted in the dominant state.
XL Frame flag, this indicates whether the frame is in XL format. This bit is always transmitted in recessive state for CAN XL frames.
For CAN FD frames, this same bit is referred to as the reserved bit ‘res’ and is always transmitted in the dominant state.
This bit does not exist in Classic CAN frames.
This bit is always transmitted in CAN XL frames as a static dominant state. This bit is reserved for future expansion of the protocol.
This represents the arbitration to data phase of the protocol. The bit rate switches from the nominal bit rate to the XL data bit rate during this phase. If a CAN SIC XL transceiver is used, it is switched into ‘fast’ mode during this phase as well.
The ADS phase provides a bit pattern with specially crafted synchronisation edges to manage the switch up to the XL data phase transfer modes.
Service Data Unit Type.
The SDT field indicates the type of data mapped onto the frame’s data field (e.g. ethernet tunnelling).
Simple Extended Context flag. The meaning of this flag is determined by the value of the SDT field.
Data Length Code. This refers to the length in bytes of the data payload contained within the frame.
For CAN XL frames, this is an 11-bit field allowing unsigned integer values of 0-2047. The actual data payload length is DLC+1, meaning that the minimum data payload length is 1 byte and maximum 2048 bytes.
Stuff bit count field. This field reports the number of dynamic stuff bits inserted into the bit stream during the arbitration phase. Valid values are 0-3.
This field is gray coded and is accompanied by an even parity bit.
Preface CRC field. This is a 13-bit CRC computed over the arbitration phase and control phase fields up until the PCRC field itself.
The calculation includes dynamic stuff bits, but excludes the fixed stuff bits and various constant bits within the bitstream (e.g. SOF, RRS, IDE, FDF, XLF, resXL, ADS).
Virtual CAN ID. This allows for a single physical CAN (XL) bus to be separated into virtual buses for multiple concurrent applications.
Acceptance Field. This field contains a 32-bit address, however the interpretation is dependent on the SDT field.
This is a variable length field that contains the data payload for the frame. The length is expected to correspond with that reported by the data length code (DLC).
Frame CRC. This is a 32-bit CRC computed over the entire frame.
The calculation excludes dynamic and fixed stuff bits, as well as other constain bits within the bitstream (e.g. SOF, RRS, IDE, FDF, XLF, resXL and ADS).
Format check pattern. This is a fixed synchronisation pattern provided to assist with the DAS phase.
This represents the switch back from the XL data phase to the last arbitration phase of the frame. The bit rate switches from the XL data bit rate to the nominal bit rate during this phase. If a CAN SIC XL transceiver is used, it is switched into ‘slow’ mode during this phase as well.
The FCP and DAS phases together provide a bit pattern with specially crafted synchronisation edges to manage the switch down from the XL data phase to arbitration phase.
During this phase, a transmitting node will send recessive bits. Receiving nodes will signal the complete and valid reception of the frame by asserting dominant bits during the ACK slot. The ACK slot is followed by an ACK delimiter bit.
End of frame.
The end of frame phase consists of seven consecutive recessive bits. Any traffic within the EOF period is regarded as an error.
Only a single differential channel is required for CAN XL decoding, however, if desired it is possible to decode using the differential signals by capturing both CAN H and CAN L and using a maths channel to compute VDIFF. The maths channel may be used as a data source for the decoder.
Once the data channel has been chosen and set up, configure the following options as per the CAN XL bus under test;
Baudrate used during the XL Data phase.
Baudrate used for the data phase of CAN FD packets with bitrate switching enabled (BRS = 1).
If no devices are present on the bus sending CAN FD packets, this field can be ignored.
Baudrate used during the arbitration phase for CAN XL packets.
This setting also applies to any Classic CAN packets and the arbitration phase of any CAN FD packets that may be present on the bus.
Selects whether the data source represents the CAN High or CAN Low signal.
If decoding CAN TXD, select CAN LOW
When all options are configured, click ‘Next’ to proceed to the Display tab.
In the Display tab, configure the following fields as required and click ‘Finish’ when done.
Sets the decoder instance name. PicoScope automatically populates this with a default name, but this can be updated as preferred.
Selects the format to be used for raw packet data displayed on the waveform graph.
Selects the format to be used for raw packet data fields in the decoder output table.
Selects whether the table displays data from all captured waveform buffers or only the currently displayed buffer.
If the time rulers are set, the decoder will only analyse data between the ruler positions.