Trigger settings for SPI bus capture

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matt.nickels
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Joined: Tue Aug 30, 2022 8:22 pm

Trigger settings for SPI bus capture

Post by matt.nickels »

I am trying to figure out the best settings to capture a sequence of exchanges on a SPI bus (Chip Select, Clock, and SDIO lines). I want to capture each individual transaction (CS low to CS high) as a waveform so each can be decoded via the serial decoder and that I don't miss any.

Unfortunately, the CS transactions vary in length (particularly on read transactions due to a variable length between the read bit/address and then the clocks that move the data). The time between transactions (CS low to next CS low) is also non-deterministic. A simple trigger on CS going low seems like it should work fine, but due to the above, depending on the time division setting, some waveforms captured have a second SPI transaction window near the end that is partially cut off. The SPI decoder recognizes it as a second "packet" but the data is not correct as part of the clock/data activity is cut off due to the waveform ending at a fixed time from the original CS trigger.

Looking for a "smarter" trigger that makes a waveform capture always be from CS low to CS high, not just from CS low for a fixed amount of time based on time divisions. Has anyone run into this and found a way to do this? Or, is there to make it capture each CS low event as a waveform even if that CS event comes in within the time the previous waveform is still being captured? Then I could just ignore all "packets > 1" in the decoder knowing that the "full" packet will also be in waveform n+1 as packet 1?

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