New protocol decoder: clocked parallel bus

17/07/21

Although, in the past few years, the trend in embedded systems design has been away from wide parallel bus communications (remember the enormous ribbon cables that were used to connect peripherals to the motherboard in desktop PCs!) to serial bus standards, there is still widespread use of clocked parallel buses in today’s devices.

Quad SPI, for example, uses four data lines. It is an extension of the classic SPI serial interface, where one or two data lines are used to read and write between devices on a PCB, or from a microcontroller to flash memory chips. Compared to classic SPI, Quad SPI increases data throughput by nearly four times, which is especially useful with memory-intensive applications. Other examples include FPGA bit-file loading interfaces such as Xilinx SelectMAP and various microcontroller BIOS bootup links.

PicoScope's parallel decoder, currently available in PicoScope 6.14.48 Beta, allows you to select up to eight data lines as well as the standard clock and chip select lines. Data present on the bus at each clock interval can be displayed on the PicoScope graph in binary, hex, decimal or ASCII formats, and can also be displayed in a table for easy correlation between the waveform and data domain.

Download the new clocked parallel bus decoders now.

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