Debugging an I²C bus with a PicoScope mixed-signal oscilloscope

AD5325 I2C decoding

Figure 1: Probe connections

This application note describes how to debug an I²C bus controlling an Analog Devices AD5325 Quad DAC using a PicoScope mixed-signal oscilloscope (MSO).

The MSO has two analog input channels, which are connected to the CH A and CH B outputs from the Quad DAC. The instrument also has 16 digital input channels. In this application only two digital input channels D0 and D1 are used, connected to the SDA serial data line and the SCL serial clock line of the I²C bus.

Two–channel I²C data transfer

Figure 2: Two–channel I²C data transfer

Display with XY cursors measuring switching amplitude and time

Figure 3: Display with XY cursors measuring switching amplitude and time

1.1  Analog display

Figure 2 shows the screen display of the PicoScope MSO. The data was acquired from an I²C bus data transfer. The display is split into three panels: the upper panel displays the two analog channels A and B plus an overview of the I²C bus transfer data. The middle panel displays two digital channels D0 and D1, and the lower panel displays the I²C decoded data.

The upper, blue trace shows the CH A output voltage switching from 1.9 V to 0.6 V. These voltage values can be read more accurately with the cursors that are available on the instrument (Figure 3). The point in time where the voltage step occurs is the end of the third byte of I²C data. This is followed by the acknowledgement bit and another transfer.

The lower, red trace shows the CH B output voltage level switching from 1.9 V to 0.6 V. The vertical scale factor for this waveform is shown in red on the right–hand side of the display. Again, the actual point when the level switches is when the DAC has received the three data bytes.

1.2  Overview of I²C data

Just below the analog waveforms, an overview of the two I²C data transfers is displayed. Each transfer contains:

  1. A START condition.
  2. The DAC address.
  3. A data byte for the channel address.
  4. Two data bytes for the channel DAC value.
  5. A STOP condition.

2.  Middle panel

This panel displays the raw digital data on the SDA serial data and SCL serial clock lines of the I²C bus. This display would show if any error in data had occurred, which could have been due to noise or interference from other signals.

It would be possible to manually decode the I²C commands from this display if the protocol of the bus were applied to each data byte, but this would be laborious and errors could easily occur. It is much faster to use the I²C decoding provided by PicoScope as displayed in the lower panel.

3.  Lower panel

This panel is the decoded I²C serial protocol display. For a clearer view of this data (Figure 5).

  • The first column is the packet number assigned by PicoScope: in this case there are 12 packets of address and data bytes plus start/stop conditions.
  • The second column shows the type of packet or event: address, data, start or stop.
  • The third column is the decoded address, in this case 0C which is the address of the DAC.
  • The next column defines if the data is a read or write. In this case both transfers were writes.
  • The fifth column displays the decoded data. In this case the first data byte 01 addresses CH A of the DAC, and 2C and 11 are the data (2C11) to be sent to the DAC to request a new output level of 1880 mV.
  • Bytes 9 and 10 show CH B was selected with data 02, and a different output level was requested by the next two bytes (2C23).
  • Column six shows that each transfer of address and data was acknowledged.
  • The final two columns indicate the timings of each transfer.

See Ref. 1 (Appendix B — References) for details of the data format expected by the AD5325 DAC.

Exported I²C data

Figure 4: Exported I²C data

4.  Exported data

The decoded I²C data can be exported to an Excel spreadsheet as shown in Figure 5.

Results from Figure 4:

Start Time Packet 3 1.011 ms
Start Time Packet 9 2.414 ms
The time difference is   1.403 ms

5.  Bus timings

Bus timing measurements can be made automatically, or manually with cursors. Figure 4 illustrates the use of cursors to measure the timing of events during data transfers. The cursors are measuring the time between the CH A and CH B voltages switching to the lower voltage level. This was measured as 1.4 ms.

A similar result could be made automatically with the timings from the decoded data. This can be seen in Figure 3 and in the same data presented in Figure 5.

6.  Trigger point

The instrument could trigger on the analog switching edge as captured on CH A, but in this case the trigger condition set was when the digital channel D0 switched to a high level, (Figure 5).

Figure 6 shows that the trigger point (t=0) occurs when the first data transfer occurs, which is the first “Start” command.

Digital trigger set up on the rising edge of D0

Figure 5: Digital trigger set up on the rising edge of D0

Multiple I²C packet transfer

Figure 6: Multiple I²C packet transfer

Sequence of I²C data transfers

Figure 7: Sequence of I²C data transfers

7.  Acquisition of multiple I²C block transfers

In more complex systems we may want to acquire multiple blocks of I²C data transfers. This can be done using the Accumulate option in the serial decode window. We will also see how PicoScope can split the acquisition memory into a number of buffers from 1 to 10,000. Each time a valid trigger condition occurs a record will be stored in a new buffer.

Figure 6 illustrates a more complex data transfer sequence. The Accumulate button in the serial decode panel is switched on and is therefore highlighted in blue. In this test 5 buffers were acquired, as shown in the top tool bar. The left and right–facing double arrows enable us to select which buffer is displayed: at present buffer 5 is displayed.

The sequence captured was five triggered I²C data transfers for five different output voltage levels. The sequence of output voltage levels requested from the two DACs is listed in Table 1.

CH A CH B
643 mV 650 mV
1885 mV 1896 mV
1015 mV 650 mV
1885 mV 1896 mV
1264 mV 650 mV

 

The sequence of commands captured and decoded for the five transfers is shown in Figure 7.

For example the command to switch the CH A output level to 1.015 V is the data transfer in the third buffer:

25 Start  
26 Address 0C select DAC
27 Data 01 select CH A
28, 29 Data 26, 80 command to switch output to 1.015 V
30 Stop  
Measuring baud rate automatically and with cursors

Figure 8: Measuring baud rate automatically and with cursors

8.  Check baud rate

The baud rate of the data transfer can be displayed in the decoded window by enabling the option in the View menu. It can also be checked by zooming in on the digital waveform display. The baud rate of this transfer was 89 kbaud and the delta cursor measurement on the digital clock D0 waveform was 11.5 µs.

9.  Conclusion

Many circuits now contain analog and digital components, so test equipment is needed that can acquire both digital and analog signals. The data from these must then be synchronized on the display window to allow in-depth analysis to locate any fault conditions in the hardware or software.

Appendix A — I²C bus

I²C Bus: What is it?

The I²C bus was designed by Philips in the early 1980s to allow easy communication between components that reside on the same circuit board. Philips Semiconductors migrated to NXP in 2006.

The name I²C stands for “Inter IC”. Sometimes the bus is called the IIC or I2C bus

The original communication speed was defined with a maximum of 100 kbit per second and many applications don’t require faster transmissions. For those that do there is a 400 kbit fastmode and—since 1998—a high speed 3.4 Mbit option available. Recently fast mode plus, a transfer rate between these, has been specified.

I²C is used not only on single boards, but also to connect components that are linked by cable. Simplicity and flexibility are key characteristics that make this bus attractive for many applications.

The most significant features include:

  • Only two bus lines required
  • No strict baud rate requirements, as for instance with RS232, since the master generates a bus clock
  • Simple master/slave relationships exist between all components
  • Each device connected to the bus is uniquely software-addressable
  • A true multi-master bus providing arbitration and collision detection

Appendix B — References

  • Analog Devices AD5305/AD5315/AD5325 Data Sheet, Rev. G, 2006.

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